Wordline latching in semiconductor memories

ABSTRACT

A memory system, and method of operation therefor, is provided having memory cells for containing data, bitlines for writing data in and reading data from the memory cells, and wordlines connected to the memory cells for causing the bitlines to write data in the memory cells in response to wordline signals. A decoder is connected to the wordlines for receiving and decoding address information in response to a clock signal and an address signal to select a wordline for a write to a memory cell. Latch circuitry is connected to the decoder and the wordlines. The latch circuitry is responsive to the clock signal for providing the wordline signal to the selected wordline for the write to the memory cell and for removing the wordline signal from the selected wordline when the write to the memory cell is complete.

BACKGROUND

1. Technical Field

The present invention relates generally to semiconductor memories andmore specifically to controlling of wordline signals.

2. Background Art

Microprocessors are used in many applications including personalcomputers and other electronic systems. A goal of any microprocessor isto process information quickly. One problem has been the communicationrate between a microprocessor and main memory. The instructions to beexecuted by the microprocessor and the data on which operationsimplemented by the instructions are to be performed are stored ataddresses within main memory. To access instructions and data, themicroprocessor transmits addresses to main memory. The main memorydecodes the address and makes the contents at the requested addressavailable for reading and/or writing. The time required for themicroprocessor to transmit an address to main memory and receive therespective contents therefrom can significantly constrain systemperformance.

One technique, which is used to increase the speed with which themicroprocessor processes information, is to provide the microprocessorwith an architecture, which includes a fast local memory called a cachememory

A cache memory is a small, fast memory that keeps copies of recentlyused data or instructions. When these items are reused, they can beaccessed from the cache memory instead of main memory. Instead ofoperating at slower main memory access speeds, the microprocessor canoperate at faster cache memory access speeds most of the time.

In order to further increase performance, microprocessors have come toinclude more than one cache memory on the same semiconductor substrateas the microprocessor.

The most commonly used cache memories use static random access memory(SRAM) circuitry, which provide high densities using wordlines andbitlines to access SRAM memory cells. However, in order to place as muchmemory on the microprocessor die as possible, SRAM circuitry requiresminimal cell and read/write circuit architectures. To support minimalarchitectures, a memory cell is accessed by enabling a row wordline wireand enabling a selected column-gating transistor to read the value fromthe memory cell.

The use of memory circuits in battery-operated and other low-voltagedevices make it desirable to operate the memory circuits at lowestvoltage possible. Typically, when read or write operations are done inmemory arrays, the wordline is set high with the power applied while theinformation stored in the memory cells is read by being transferred ontobitlines or information on the bitlines is written by being stored inthe memory cells. For read operations, bitlines are then read by asense-amplifier, or sense-amp. Sense-amps are common to all memorieswhether the memories are dynamic, static, Flash, or other types ofmemories. For write operations, information on the bitlines change theheld charge in the memory cell. While the wordline is kept on, power isbeing consumed. The wordline remains on during and after the desiredoperation, whether it is a read or a write, to ensure the operation iscomplete; i.e., power is consumed even when no longer required.

Reading reliable results from memory circuits operating at a low-powersupply voltage is complicated by the large capacitance of the wordlinesand the threshold drop produced by the gating transistor. Low-powersupply voltages reduce memory speed, and at very low voltages, thereliability of the information drops.

To address the reliability problem, memory circuits, which have abootstrapped boost voltage applied to the wordlines, have beendeveloped. The row wordline is charged to a voltage that is higher thanthe power supply line. In addition, the row wordline is charged prior toaccessing the memory location by switching on the column-gatingtransistor. Boost circuits provide reliable memory operation at lowvoltages.

One of the problems with boost circuits is that at high voltages, theaccess circuitry is over-stressed. This limits the upper end of thepower supply operating range of a memory device.

Another problem is that boosting increases the power consumption of amemory circuit. At high supply voltages, the power dissipation canexceed tolerable levels and the memory circuitry is subject to failuresdue to overheating.

Power saving has been a persistent need. Because low-power consumptionis becoming even more important, it is desirable to provide a method andapparatus for operating a memory device in a manner that saves power.Furthermore, it is desirable to achieve reliable read and writeoperations at low voltages.

With the urgency of increasing speed and saving power, solutions tothese problems have been long sought but have long eluded those skilledin the art.

DISCLOSURE OF THE INVENTION

The present invention provides a memory system, and method of operationtherefor, having memory cells for containing data, bitlines for writingdata in and reading data from the memory cells, and wordlines connectedto the memory cells for causing the bitlines to write data in the memorycells in response to wordline signals. A decoder is connected to thewordlines for receiving and decoding address information in response toa clock signal and an address signal to select a wordline for a write toa memory cell. Latch circuitry is connected to the decoder and thewordlines. The latch circuitry is responsive to the clock signal forproviding the wordline signal to the selected wordline for the write tothe memory cell and for removing the wordline signal from the selectedwordline when the write to the memory cell is complete. The memorysystem conserves power while permitting reliable read and writeoperations at low voltages.

Certain embodiments of the invention have other advantages in additionto or in place of those mentioned above. The advantages will becomeapparent to those skilled in the art from a reading of the followingdetailed description when taken with reference to the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an SRAM in accordance with the presentinvention;

FIG. 2 is a timing diagram showing operative signals in accordance withthe present invention;

FIG. 3 is a schematic diagram of a memory circuit in accordance with thepresent invention;

FIG. 4 is a timing diagram of a read-only operation in accordance withthe present invention; and

FIG. 5 is a timing diagram of the read-write operation in accordancewith the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Referring now to FIG. 1, therein is shown a block diagram of an SRAM100, with core regions typically including one or more M×N arrays 104 ofindividually addressable, substantially identical memory cells.Peripheral portions typically include input/output (I/O) circuitry andprogramming circuitry for selectively addressing the individual memorycells in accordance with the present invention. The cell accesscircuitry is represented in part by and includes one or more x-decoders108 and y-decoders 110, cooperating with I/O circuitry 106 forconnecting the source, gate, and drain of selected addressed memorycells to predetermined voltages or impedances to effect designatedoperations on the memory cell, e.g., programming, writing, reading,erasing, and deriving necessary voltages to effect such operations.

Referring now to FIG. 2, therein is shown is a timing diagram 300 havinga vertical voltage axis and a horizontal time axis. A clock signal 310and two wordline signals 312 and 314 are shown in accordance with thepresent invention. The clock signal 310 is cyclic and a full cycle andpart of a subsequent cycle are shown. The clock signal 310 also has twophases: Phase A and Phase B measured from about the middle of the riseand fall times such that the clock signal 310 is going high to a digitalone in the beginning of Phase A, low to a digital zero in the beginningof Phase B, and high to a digital one in the beginning of the nextsubsequent phase. The wordline signal 312 shows the duration duringwhich a wordline signal remains at a high voltage, or high, on awordline for a read-only operation. The wordline signal 314 shows theduration during which a wordline signal remains latched high on awordline for a read-write operation to respectively read data in andwrite data to a memory cell.

A time delay 316 is shown because the wordline signals 312 and 314 aretriggered by the beginning of the clock signal 310 but are delayed inreaching the wordlines because of decoding and other processes requiredbefore the wordline signals 312 and 314 can be imposed on the wordlines.The various signals overlap at various times and voltages but are shownoffset in FIG. 2 in the interests of clarity. This is true for all thetiming diagrams herein.

The present invention can be applied to read-modify write schemes wherewrite operations are performed after read operations. In certainembodiments of the present invention, read and write operations canoccur in a single clock cycle. Accordingly, read operations from the M×Ncell array 104 of FIG. 1 occur during both read-only operations andwrite operations.

For a read-only operation, the wordline signal goes high ideally at thestart of Phase A as shown by the wordline signal 312. The read operationis triggered by a falling clock edge of the clock signal 310. Accordingto the present invention, the wordline signal 312 is shut down as soonas possible after the read operation to conserve power since power isbeing consumed whenever the wordline signal is being provided

If a write operation is desired, the wordline signal goes high ideallyat the start of Phase A as shown by the wordline signal 314 and isextended throughout Phase B so that the write operation can occur withinPhase B. However, the wordline signal 314 is unlatched and shut down assoon as possible after Phase B to conserve power.

Referring now to FIG. 3, therein is shown a schematic diagram of awordline latching memory circuit 400 in accordance with the presentinvention. A clock 401 is connected to clock inputs of a set of addressflip-flops 402. The set of address flip-flops 402 include one or moreaddress flip-flops 402(1 . . . n) for 1 . . . n wordlines. In oneembodiment, the address flip-flops 402(1 . . . n) are monotonic, or incontinuous sequence, and each provide true and complementary outputs.

The set of address flip-flops 402 is connected to a decoder 406, whichcauses the time delay 316 of FIG. 2. The decoder 406 includes decodingcircuits 408(1 . . . n) for decoding address information. Each of thedecoding circuits 408(1 . . . n) includes a pair of NAND gates 410(1 . .. n) and 412(1 . . . n), which have outputs respectively coupled to aninput of AND gates 414(1 . . . n), which have respective outputsconnected to an input of inverters 416(1 . . . n). The outputs of theinverters 416(1 . . . n) are the outputs of the decoder 406.

The decoder 406 can be of several types such as static decoders (shownon FIG. 3), dynamic decoders, or two-bit pre-decoders.

The decoder 406 connects to latch circuitry 418. The latch circuitry 418includes a set of OAI gates 420(1 . . . n), which are respectivelyconnected to the inverters 416(1 . . . n) of the decoder 406. The numberof OAI gates 420 can vary depending on the specific application, butgenerally it is equal to the number of wordlines. For example, the OAIgates 420(1 . . . n) are respectively connected to wordlines 422(1 . . .n). The decoder 406 decodes the address information to select thewordlines 422(1 . . . n), which will be activated when they have beenselected.

Each of the OAI gates 420(1 . . . n) includes an OR gate 424(1 . . . n)and an AND gate 426(1 . . . n). Each of the outputs from the inverters416(1 . . . n) respectively connects to first inverting inputs of the ORgate 424(1 . . . n), and each of the outputs of the AND gate 426(1 . . .n) respectively connects to second inverting inputs of the OR gates424(1 . . . n). The outputs of the OR gates 424(1 . . . n) are therespective output of the OAI gates 420(1 . . . n) to the wordlines 422(1. . . n). The outputs of the OR gate 424(1 . . . n) also respectivelyconnect to first inputs of NAND gates 428(1 . . . n). The NAND gates428(1 . . . n) have respective outputs connected to first invertinginputs of the AND gate 426(1 . . . n). Second inverting inputs of theAND gate 426(1 . . . n) are connected to the clock 401.

The clock 401 also connects to a write-enable flip-flop 430, whichresponds to a write-enable signal 531 and has an output that connects tosecond inputs of the NAND gates 428(1 . . . n).

The wordlines 422(1 . . . n) are respectively connected to a set ofmemory cells 432 having memory cells 432(1 . . . n). The memory cells432(1 . . . n) respectively include two pass transistors 434(1 . . . n)and 436(1 . . . n) having gates to which the wordlines 422(1 . . . n)are respectively connected. The two pass transistors 434(1 . . . n) and436(1 . . . n) are respectively coupled to two inverters 438(1 . . . n)and 440(1 . . . n) and to two bitlines 442 and 444. It will beunderstood that there will be a plurality of bitlines in the cell array104, but only two are shown.

The two bitlines 442 and 444 are connected to sensing circuitry such asa sense-amp 450. The sense-amp 450 is one of a plurality of sense-ampsconnected across the respective plurality of bitlines. The write-enableflip-flop 430 connects to a first inverting input of a read-enable ANDgate 452 and the output of the read-enable AND gate 452 connects to thesense-amp 450 (and to other sense-amps for the other bitlines). A secondinverting input of the read-enable AND gate 452 is connectable receiveto an enable signal 454.

Referring now to FIG. 4, therein is shown a timing diagram 500 having avertical voltage axis and a horizontal time axis. The timing diagram 500is for a read-only operation. The clock signal 310 is shown with thewordline signal 312, which represents the duration in which a wordlinesignal remains high for the read-only operations. In accordance with thepresent invention, two bitline signals 502 and 504 are shown. Thebitline signals 502 and 504 represent signals on the bitlines such asthe bitlines 442 and 444 of FIG. 3, respectively. A vertical line 506represents the approximate trigger point of the sense-amp 450.

The wordline signal 312 rises shortly after the clock signal 310 rises,due to the time delay 316. When the wordline signal 312 goes high, adifferential builds. The bitline signal 502 stays high all the timebecause it is connected to a high voltage side of the memory cell 432(1)of FIG. 3. The bitline signal 504 slowly drops and is connected to thelow voltage side of the memory cell 432; there is typically a 0 voltageat that point. Accordingly, there is a small voltage differentialbetween the bitline signals 502 and 504 indicative of a logical state ofthe memory cell 432(1). In order for the overall circuit to operateproperly the differential must be amplified so that the signal goes fromzero to high. The sense-amp 450 amplifies the differential to provide aso-called full-swing voltage. The bitline signal 504 lowers in voltagedue to a capacitance on the transistor 436(1) of FIG. 3. The transistor436(1) of FIG. 3 has capacitance switch discharges causing the bitlinesignal 504 to lower in voltage.

The bitline signal 504 begins to rise again after the wordline signal312 goes low. As the wordline signal 312 goes low, the bitline signal504 is not being pulled down. So the bitline signal 504 gets chargedback up. The bitline signal 504 is charged back up because the bitlinesignal 504 is always connected to a Vdd voltage source (not shown). Avertical line represents an approximate sense-amp trigger point 506 ofthe sense-amp 450. This trigger point is important where the wordlinelatch circuit is a synchronous design, as it is in this specificembodiment. Because it is synchronous, events occur on the falling orrising edge of the clock cycle, subject to some delays; e.g., by thedecoder delay.

During a write operation, the wordline 422(1) goes low immediately afterthe write operation completes by using the falling edge of the clocksignal 310 to release the latch of the wordline signal 314. If thewordline 422(1) goes low too soon, a write signal 603 to the bitlines442 and 444 will not be able to write to the memory cell 432(1) becauseit will be shut off.

Referring now to FIG. 5, therein is shown a timing diagram 600 having avertical voltage axis and a horizontal time axis. The timing diagram 600is for a write operation. The clock signal 310 and bitline signals 602and 604 are shown in accordance with the present invention. During thewrite operation in the Phase B, the memory cell 432(1) is turned on;i.e., the pass transistors are turned on, connecting memory cell to thebitlines. The wordline signal 314 shows the duration in which thewordline signal 314 remains high for write operations.

The operation of wordline latching memory circuit 400 is hereinafterdescribed with reference FIGS. 3-5.

The address signals enter the address flip-flops 402(1 . . . n) timed bythe clock signals 310 from the clock 401. When the clock 401 is assertedhigh, the set of address flip-flops 402 is triggered creating a set oftrue and complimentary signals that are fed to the decoder 406. Theaddress flip-flops 402(1 . . . n) selectively enable or disable thewordlines 422(1 . . . n) by providing selected signals to the groups ofsix inputs of the decoding circuits 408(1 . . . n) in the decoder 406.

The following is an example of the operation of the wordline latchingmemory circuit 400 for a single wordline.

For a read-only operation, when the decoder 406 determines the wordline422(1) has been selected, the NAND circuit 408(1) outputs a low to theOAI gate 420(1). In the OAI gate 420(1), the inverting input of OR gate424(1) is pulled low causing the output of OAI gate 420(1) to rise asshown by the wordline signal 312.

The write-enable signal 431 is held low so the output of thewrite-enable flip-flop 430 is also forced low upon being triggered bythe clock signal 310 from the clock 401. This forces the output of NANDgate 428(1) to be high, effectively disabling the AND gate 426(1) andcausing the OAI gate 420(1) to provide a high on to the wordline 422(1).The high on the wordline 422(1) activates the memory cell 432(1) toplace bitline signals 502 and 504, representative of previously storedhigh or lows signals, to be transferred onto the bitlines 442 and 444.

When the clock signal 310 falls, the outputs of the address flip-flops402(1 . . . n) are forced low to conserve power but the wordline signal312 remains high because of the time delay 316.

The read operation is performed while the wordline signal 312 is highand after the clock signal 310 reaches its low at the approximatesense-amp trigger point 506. The sense-amp 450 is triggered by the clocksignal 310 and the enable signal 454 via the read-enable AND gate 452 toread the bitlines 442 and 444 for the bitline signals 502 and 504. Thesense-amp 450 latches the data from the bitline signal 504 from thebitline 444.

Shortly after the triggering of the sense-amp 450, the wordline signal312 falls to its low.

For a read, the effective power cut-off to all the wordlines around thebeginning of the falling edge of the clock signal 310 conserves powerand the read at around the end of the falling edge of the clock signal310 assures the security of the read operation.

The operation of the wordline latching memory circuit 400 for the writeoperation is similar to that of the read operation. The main differenceis that the wordline is being held high longer, but not so long that itinterferes with the next clock cycle.

For a write operation, when the decoder 406 determines the wordline422(1) has been selected, the NAND circuit 408(1) outputs a low to theOAI gate 420(1). In the OAI gate 420(1), the inverting input of OR gate424(1) is pulled low causing the output of OAI gate 420(1) to rise asshown by the wordline signal 314.

The write-enable signal 431 is held high so the output of thewrite-enable flip-flop 430 is also forced high upon being triggered bythe clock signal 310 from the clock 401. This forces the output of NANDgate 428(1) to be low, enabling the AND gate 426(1) and causing the OAIgate 420(1) to provide a high on to the wordline 422(1). The high on thewordline 422(1) activates the memory cell 432(1) to place the bitlinesignals 502 and 504, representative of previously stored high or lowssignals, onto the bitlines 442 and 444.

When the clock signal 310 falls, the outputs of the address flip-flops402(1 . . . n) are forced but the wordline signal 314 remains high evenwhen the decoder 406 provides a low to the OAI gate 420(1). With thewrite-enable flip-flop 430 providing a high and the OAI gate 420(1)providing a high, the NAND GATE 428(1) provides a low to the firstinverting input of the AND gate 426(1) while the clock 401 provides asecond low to the second inverting input. As a result, the AND gate426(1) provides a high to the OR gate 424(1) to latch the wordline422(1) in high.

The read operation can optionally be performed during Phase A.

The write operation is performed while the wordline signal 314 is stillhigh in Phase B as indicated by the write pulse placed on the bitline442 by the bitline signal 602 from the I/O circuitry 106 of FIG. 1.

The combination of the NAND gate 428(1) and the OAI gate 420(1) forms alatch which holds the wordline 422(1) high until the clock signal 310starts rising again causing AND gate 426(1) to unlatch the output of theOAI gate 420(1) and de-assert the wordline 422(1).

For a write, the effective power cut-off to all the wordlines around thebeginning of the rising edge of the clock signal 310 assures the safetyof the successful read operation in the next cycle.

Embodiments of the present invention can have several applications. Insome applications the wordline latch circuit can be used in cachememory. Typically, cache memories are built of one or more smallermemory blocks called banks. The wordline latch circuit can be usedinside the banks of cache memory. Other embodiments can be used outsideof cache memory as well.

When used in a microprocessor for example, the microprocessor generatesthe memory addresses where the data resides. The microprocessor can haveseveral layers of memory. There is a so-called Level 1 (L1) memory and aLevel 2 (L2) memory, sometimes a Level 3 (L3) memory. There is also amain memory. The main memory is also called external memory because itis typically external to the microprocessor. L1 memory is the easiestand fastest memory to access. When the microprocessor looks for data itwill typically start with L1 memory, then will go to L2 memory, then L3memory, and finally to the main memory.

If the microprocessor fetches data from the main memory it could takeabout 100-150 clock cycles to fetch. This is slow compared to 1 to 2clock cycles that would be required to fetch data from the cache memory.Thus there are compelling reasons to have data stored on the chipitself.

While the invention has been described in conjunction with a specificbest mode, it is to be understood that many alternatives, modifications,and variations will be apparent to those skilled in the art in light ofthe aforegoing description. Accordingly, it is intended to embrace allsuch alternatives, modifications, and variations which fall within thespirit and scope of the included claims. All matters hither-to-fore setforth herein or shown in the accompanying drawings are to be interpretedin an illustrative and non-limiting sense.

The invention claimed is:
 1. A memory system comprising: memory cellsfor containing data; bitlines to write data in and read data out fromthe memory cells; wordlines connected to the memory cells for causingthe bitlines to write data in the memory cells in response to wordlinesignals; a decoder connected to the wordlines to receive and decodeaddress information in response to a clock signal and an address signalto select a wordline for a write to a memory cell; latch circuitryconnected to the decoder and the wordline and having a first gate toprovide a wordline signal in response to the clock signal, the latchcircuitry having a second gate connected to the first gate and thewordline, the second gate responsive to a write-enable signal and thewordline signal to provide a signal to the first gate.
 2. The memorysystem as claimed in claim 1 wherein: the first gate is a OR-AND-Invertgate; and the second gate is a NAND gate.
 3. The memory system asclaimed in claim 1 including: write-enable circuitry connected toreceive the clock signal and an initiate write signal to provide thewrite-enable signal in response to the clock signal.
 4. The memorysystem as claimed in claim 1 including: sensor circuitry connected tothe bitlines to read data from the memory cells in response to aread-enable signal; and read-enable circuitry connected to the sensorcircuitry to receive the clock signal and responsive an initiate readsignal and the clock signal to provide the read-enable signal.
 5. Thememory system as claimed in claim 1 including: a clock providing theclock signal, the clock signal is a cyclic signal having rising andfalling edges in each cycle.
 6. A memory system comprising: memory cellsfor containing data; bitlines for writing data in and reading data fromthe memory cells; wordlines for causing the bitlines to write data inthe memory cells in response to wordline signals; a decoder to receivedecode address information in response to a clock signal and an addresssignal to select a wordline for a write to a memory cell, the decoder isresponsive to the clock signal having rising and falling edges, thedecoder responsive to the rising edge to start the decode and thefalling edge to stop the decode; and latch circuitry responsive to theclock signal to provide the wordline signal to the selected wordline forthe write to the memory cell and to remove the wordline signal from theselected wordline when the write to the memory cell is complete, thelatch circuitry is responsive to the falling edge and a write-enablesignal to latch the wordline signal on the selected wordline for thewrite to the memory cell, the latch circuitry responsive to the secondrising edge to unlatch the wordline signal from the selected wordline.7. A memory system comprising: memory cells for containing data;bitlines for writing data in and reading data from the memory cells;wordlines for causing the bitlines to write data in the memory cells inresponse to wordline signals; a decoder to receive and decode addressinformation in response to a clock signal and an address signal toselect a wordline for a write to a memory cell, the decoder isresponsive to the clock signal having rising and falling edges, thedecoder responsive to the raising edge to start the decode and thefalling edge to stop the decode; latch circuitry responsive to the clocksignal to provide the wordline signal to the selected wordline for thewrite to the memory cell and to remove the wordline signal from theselected wordline when the write to the memory cell is complete; andsensor circuitry connected to the bitlines and responsive to the fallingedge and a read-enable signal to read data from the memory cells.
 8. Amemory system comprising: memory cells for containing data; bitlines forwriting data in and reading data from the memory cells; wordlines forcausing the bitlines to write data in the memory cells in response towordline signals; a decoder to receive and decode address information inresponse to a clock signal and an address signal to select a wordlinefor a write to a memory cell; latch circuitry responsive to the clocksignal to provide the wordline signal to the selected wordline for thewrite to the memory cell and to remove the wordline signal from theselected wordline when the write to the memory cell is complete; and aclock providing the clock signal, the clock signal having rising andfalling edges wherein: the decoder is responsive to the onset of theraising edge to start the decode and the onset of the falling edge tostop the decode; and the latch circuitry is responsive to the middle ofthe falling edge and a write-enable signal to latch the wordline signalon the selected wordline for the write to the memory cell, the latchcircuitry responsive to the middle of the second rising edge to unlatchthe wordline signal from the selected wordline.
 9. The memory system asclaimed in claim 6 wherein: the latch circuitry includes circuitry toprovide the wordline signal to the selected wordline for a read of thememory cell and to remove the wordline signal from the selected wordlinewhen the read of the memory cell is complete.
 10. The memory system asclaimed in claim 7 wherein: the latch circuitry includes circuitry toprovide the wordline signal to the selected wordline for a read of thememory cell and to remove the wordline signal from the selected wordlinewhen the read of the memory cell is complete.
 11. The memory system asclaimed in claim 8 wherein: the latch circuitry includes circuitry toprovide the wordline signal to the selected wordline for a read of thememory cell and to remove the wordline signal from the selected wordlinewhen the read of the memory cell is complete.
 12. A method for memorysystem operation comprising: providing memory cells for containing data;writing data in and reading data from the memory cells on bitlines;responding to wordline signals on wordlines by causing the bitlines towrite data in the memory cells; selecting a wordline for a write to amemory cell using a decoder for receiving and decoding addressinformation in response to a clock signal and an address signal;responding to the clock signal and selecting a wordline for providing awordline signal using a first gate; and responding to a write-enablesignal and the wordline signal to provide a latch signal to the firstgate using a second gate.
 13. The method for memory system operation asclaimed in claim 12 wherein: responding to the clock signal andselecting a wordline uses the first gate having a OR-AND-Invert gate;and responding to a write-enable signal and the wordline signal uses thesecond gate having a NAND gate.
 14. The method for memory systemoperation as claimed in claim 12 wherein: responding to the write-enablesignal uses a write-enable circuitry for receiving the clock signal andan initiate write signal for providing the write-enable signal.
 15. Themethod for memory system operation as claimed in claim 12 including:reading data from the memory cells in response to a read-enable signalusing sensor circuitry connected to the bitlines; and receiving theclock signal and an initiate read signal to provide the read-enablesignal using read-enable circuitry connected to the sensor circuitry.16. The method for memory system operation as claimed in claim 12including: providing the clock signal provides a cyclic signal havingrising and falling edges in each cycle.
 17. A method for memory systemoperation comprising: providing memory cells for containing data;writing data in and reading data from the memory cells on bitlines;responding to wordline signals on wordlines by causing the bitlines towrite data in the memory cells; selecting a wordline for a write to amemory cell using a decoder for receiving and decoding addressinformation in response to a clock signal and an address signal,selecting the wordline includes responding to rising edge of the clocksignal by the decoder to start decoding and a falling edge of the clocksignal to stop decoding; and latching a wordline signal in response tothe clock signal by providing the wordline signal to the selectedwordline for the write to the memory cell and for unlatching thewordline signal from the selected wordline when the write to the memorycell is complete, latching the wordline signal includes: responding tothe falling edge and a write-enable signal by latching the wordlinesignal on the selected wordline for writing to the memory cell; andresponding to the second rising edge by unlatching the wordline signalfrom the selected wordline.
 18. A method for memory system operationcomprising: providing memory cells for containing data; writing data inand reading data from the memory cells on bitlines; responding towordline signals on wordlines by causing the bitlines to write data inthe memory cells; selecting a wordline for a write to a memory cellusing a decoder for receiving and decoding address information inresponse to a clock signal and an address signal selecting the wordlineincludes responding to the clock signal having a rising and fallingedges to start decoding on the raising edge and to stop decoding on thefalling edge; latching a wordline signal in response to the clock signalby providing the wordline signal to the selected wordline for the writeto the memory cell and for unlatching the wordline signal from theselected wordline when the write to the memory cell is complete; andresponding to the falling edge and a read-enable signal for reading datafrom the memory cells by sensor circuitry.
 19. A method for memorysystem operation comprising: providing memory cells for containing data;writing data in and reading data from the memory cells on bitlines;responding to wordline signals on wordlines by causing the bitlines towrite data in the memory cells; selecting a wordline for a write to amemory cell using a decoder for receiving and decoding addressinformation in response to a clock signal and an address signal;latching a wordline signal in response to the clock signal by providingthe wordline signal to the selected wordline for the write to the memorycell and for unlatching the wordline signal from the selected wordlinewhen the write to the memory cell is complete; and providing the clocksignal having rising and falling edges including: responding to themiddle of the raising edge to start decoding and the middle of thefalling edge to stop decoding by the decoder; and responding to themiddle of the falling edge and a write-enable signal for latching thewordline signal on the selected wordline for the writing to the memorycell and responding to the middle of the second rising edge forunlatching the wordline signal from the selected wordline.
 20. Themethod for memory system operation as claimed in claim 17 including:providing the wordline signal to the selected wordline for reading ofthe memory cell and removing the wordline signal from the selectedwordline when the reading of the memory cell is complete.
 21. The methodfor memory system operation as claimed in claim 18 including: providingthe wordline signal to the selected wordline for reading of the memorycell and removing the wordline signal from the selected wordline whenthe reading of the memory cell is complete.
 22. The method for memorysystem operation as claimed in claim 19 including: providing thewordline signal to the selected wordline for reading of the memory celland removing the wordline signal from the selected wordline when thereading of the memory cell is complete.